The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. Design structure is preferably an input to a design process and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Gate has node 36 as one of its input and turns devices 28 and device 24 off by pulling node to low. The invention relates generally to a bootstrap circuit, and more particularly to, a word line bootstrap circuit for implementing a high-speed flash memory and a memory cell having a good data holding capability. After a sufficient discharge of the load, device 40 is turned off but device 28 is turned on, making device 32 a diode. The negative substrate bias makes nmos devices handle negative voltages during the boosting phase of the wordline clock.

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One of the latch outputs controls the inverter stage and the other controls the first FET.

USB1 – Bootstrap circuit – Google Patents

boptstrap This results in that the n-channel type field effect transistor Qn61 to turn on, bootshrap current flows through the voltage level adjusting circuit 33b so that the second predetermined voltage level takes place at the node N It should be understood that the present invention is not limited to the illustrated wordline driver and decoder SRAM circuit with only one group of wordlines.

When Node N2 is down, T6 turns on and connects the associated terminal of the capacitor N3 is now the negatively charged terminal of Cb to Vcc.

Further, the supply voltage transfer unit further includes sixth and seventh PMOS transistors P 6 and P 7 which are connected between the supply voltage Vcc source and the second resistor R 2 in parallel and driven by the output signal of the first inverter I 1 for inverting an external driving signal ATD. The time delay determines the discharging time of the load and is easily changed by adding an even number of inverters between inverter 68 and gate The low state at node 70 ripples through the inverter chain,, and In accordance with features of the invention, the increased wordline voltage generated by the wordline voltage boosting circuit improves read access time and write time of the SRAM.

Fourth and fifth FETs are connected to receive a timing signal and to produce true and complement phases for controlling the latch.

This in turn bumps the node 96 up because of the capacitive coupling through capacitor With the output signal of logic “0”, the inverting circuit IN60 shifts the third controlling signal CNT3 from the ground voltage level to the power voltage level Vcc, and the n-channel type field effect transistor Qn61 allows current to pass through the voltage level adjusting circuit 33b.


Thus, there is a trade-off between the protection of the extremely thin gate oxide films and the current consumption, and the problems are inherent in the prior art bootstrap circuit incorporated in the random access memory device.

Wordlin wordline voltage boosting circuit as recited in claim 1wherein said bootstrap capacitor is shared across a group of wordline drivers, minimizing required chip area for the wordline voltage boosting circuit.

This results in that the node N37 with the power voltage level Vcc discharges electric charges through the p-channel type field effect transistor Qp40 and the n-channel type field effect transistor Qn61 to the ground node, and the other electrode of the bootstrap capacitor C31 is decayed to the second predetermined voltage level.

The inverting circuit IN4 allows the voltage level at the output node N4 to start on rising at time t4, and the output node N2 is boosted over the power voltage level Vcc through the bootstrapping of the capacitor C1 cooperating with the load capacitor C2 without any substantial time delay from time t4. A object of the present invention is to provide a semiconductor memory clock circuit for boosting the wordline voltage.

Design structure may then proceed to a stage where, for example, design structure proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, and the like. Also, the wordline voltage boosting circuit enables improved performance without introducing a second power supply, which decreases the system cost.

The switching unit is coupled to the constant voltage source and to the bootstrap unit. Node 26 is at GND but device 32 is off, preventing the load from discharging to the ground. This turns device 28 on but turns wordlihe 40 off.

Low Power Spin-Transfer Magnetoresistive Random Access Memory Writing Scheme wit

A bootstrap circuit as set forth in claim 15, in which the second discharging controller comprises a sixth inverting circuit having an input node coupled to an output node of the comparator circuit and a seventh inverting circuit having an input node supplied with the one-shot pulse signal, and a second NOR gate having input nodes coupled to output nodes of the tenth and eleventh inverting circuits for producing the second discharging signal.


The inverting circuit IN33 causes the complementary input signal CSin to start on rising at time t12, and the output node N32 follows the complementary input signal CSin. With device 28 on, device 32 is in a diode configuration. Integrated semiconductor memory with internal voltage booster of lesser dependency on power supply voltage.

It can be seen from FIG. Thus, the conventional bootstrap circuit has problems that not only a margin of the word line voltage could not be secured but also the target specification range could not be secured. Then, the comparing circuit CM is activated, and compares the voltage level at the node N71 with the second predetermined voltage level.

The circuit operates as follows. The power voltage level and the ground voltage level are assumed to be logic “1” level and logic “0” level, respectively, and both of the NOR gates NR61 and NR62 usually produce respective output signals of logic “0” level, because logic “1” level and logic “0” level are supplied to the input nodes of each NOR gate NR61 or NR Second and third FETs form a latch that has one output connected to control the inverter stage and the other output connected to control the first FET.

US6559707B1 – Bootstrap circuit – Google Patents

For this reason, the clamping circuit 2 restricts the voltage level at the output node N2 in a high voltage level Vh’ between the power voltage level and the higher voltage level Vh, and the voltage level at the output node N2 traces real line RL instead of the broken lines BL. The bootstrap circuit according to the present invention saturates the output voltage level around the first predetermined voltage level through the bootstrxp phenomenon, and the clamping circuit 32 is provided for canceling excess electric charges supplied from the charge pump unit 30 only.

The one-shot pulse signal and the wordpine signal thereof produced by the inverting circuit IN76 boootstrap the field effect transistors Qp73 and Qn74 to turn on to couple the comparing circuit CM to the source of power voltage level Vcc and the ground node.

Therefore, though a target specification of a general word line voltage must be swung within 1V, the swing range of the boosting voltage Vboot in the conventional bootstrap circuit is about 1.